A consortium of Scottish companies and academic organisations is looking for an investment bank to participate in a programme designed to demonstrate the effectiveness of FPGA (Field Programmable Gate Array) technology in reducing power consumption in high performance applications.
The FPGA High Performance Computing Alliance (FHPCA) - which comprises seven organisations and is funded by Scottish Enterprise - has already engaged with companies in the the oil & gas, medical, aerospace and civil engineering sectors to port suitable applications to a purpose-built FPGA machine housed at the University of Edinburgh.
Commercially available reconfigurable FPGA-based computers have been available for some time. However, it is only now that they are becoming cost effective in the high performance computing marketplace and significant investment in the technology is being made by all of the major hardware vendors. A number of investment banks - among them Credit Suisse - have already started experimenting with the technology in an effort to slow energy consumption in the data centre.
Building large FPGA-based systems is not difficult, says the Edinburgh consortium, however programming them is. The FHPCA's aim is to to develop a toolkit and parallelisation expertise to ease the porting of existing numerically intensive applications to such systems.
"Only by basing the work on real applications can we ensure the resulting toolkit is applicable in a wide variety of real-world computing scenarios," says the group.
To this end, the FHPCA is looking to engage with a financial services organisation to identify and assess a suitable number-crunching application for porting to the FPGA demonstrator system. The partner bank - which will not be expected to make any financial contribution to the project - will be able to access the sytem direct and assess the efficiency of the approach.
The FPGA demonstrator system has been under development for 18 months as has the Parallel Toolkit software. It will be completed in October 2006 and will consist of 64 tightly coupled Xilinx Virtex 4 FPGAs hosted in a 32 processor IBM eServer Bladecenter Chassis. This system should be capable of around a Teraflop.
The aim is to commence evaluation of an appropriate code in October 2006